The present invention relates generally to the preparation of semiconductor devices and more particularly to improved slurry compositions for the chemical-mechanical planarization (CMP) of metal (e.g., Cu) layers and barrier materials (e.g., Ta, TaN, etc.) and dielectric materials.
A semiconductor wafer typically includes a substrate, such as a silicon wafer, on which a plurality of integrated circuits has been formed. In the manufacture of integrated circuits, wafer surface planarity and quality is of extreme importance. In order to achieve the degree of planarity required to produce ultra high-density integrated circuits, CMP processes are being employed.
In general, CMP involves pressing a semiconductor wafer against a moving polishing surface that is wetted with a chemically reactive, abrasive slurry. Conventional slurries either are acidic or basic, and generally contain alumina, silica, zirconium oxide, magnesium oxide, or cerium oxide abrasive particles. The polishing surface usually is a planar pad made of a relative soft, porous material, such as polyurethane. The pad usually is mounted on a planar platen. Continuous pad devises also are being tested. Systems devoid of a slurry where the pad contains the abrasive also are being used.
Integrated circuits are chemically and physically integrated into a substrate by patterning regions in the substrate and layers on the substrate. The layers generally are formed of various materials either having a conductive, insulating, or semiconducting nature. Also, barrier materials or barriers are used to prevent the migration of ions and adhesion promoters. In order for a device to have high yields, it is crucial to start with a flat semiconductor wafer. If the surface is not uniform (e.g., areas of unequal elevation or surface imperfections), various problems can occur which may result in a large number of inoperable devices. Further in this regard can be found in the following references: Luo, et al., "Chemical-Mechanical Polishing of Copper: A Comparative Analysis," Feb. 13-14 CMP-MIC Conference, 1997 ISMIC - 200:/97/0083; Babu, et al, "Some Fundamental and Technological Aspects of Chemical-Mechanical Polishing of Copper Films: A Brief Review," Feb. 19-20, 1998 CMP-MIC Conference, 1998 IMIC - 300P98/0385; Tseng, et al., "Effects of mechanical characteristics on the chemical-mechanical polishing of dielectric thin films," Thin Solid Films, 290-291 (1996) 458-463; Nanz, et al., "Modeling of Chemical-Mechanical Polishing: A Review," IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No. 4, November 1995; Stiegerwald, et al., "Pattern Geometry Effects in the Chemical-Mechanical Polishing of Inlaid Copper Structures,": "J. Electrom. Soc., Vol 141, No. 10, October 1994 ; Fury, "Emerging developments in CMP for semiconductor planarization--Part 2,"Solid State Technology, 81-88, July 1995; Fury, "CMP Standards: A Frustration Cure," Semiconductor International, November 1995.
Despite CMP being commercially practice, there still are a number of problems including, for example, non-uniformity in material removal rate, Cu dishing, oxide erosion, Cu line corrosion, field oxide thinning, and other surface defects. Thus, there exists a need in CMP for improvements.